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1 features ? write protect pin for hard ware data protection ? utilizes different array protection compared to the at24c02b low-voltage and standard-voltage operation ? 1.8 (v cc = 1.8v to 5.5v) internally organized 256 x 8 (2k) two-wire serial interface schmitt trigger, filtered inputs for noise suppression bidirectional data transfer protocol 1 mhz (5v) and 400 khz (1.8v, 2.5v, 2.7v) clock rate 8-byte page partial page writes allowed self-timed write cycle (5 ms max) high reliability ? endurance: one million write cycles ? data retention: 100 years 8-lead pdip, 8-lead jedec soic and 8-lead tssop packages die sales: wafer form, waffle pack, and bumped wafers description the at24hc02b provides 2048 bits of serial electrically erasable and programmable read-only memory (eeprom) orga nized as 256 words of 8 bits each. the device is opti- mized for use in many industrial and commerc ial applications where low-power and low- voltage operation are essential. the at24hc02b is available in space-saving 8-lead pdip, 8-lead jedec soic and 8-lead tssop packages and is accessed via a two-wire serial interface. in addition, the entire family is available in 1.8v (1.8v to 5.5v) version. table 1. pin configuration pin name function a0?a2 address inputs sda serial data scl serial clock input wp write protect nc no-connect two-wire serial eeprom 2k (256 x 8) at24hc02b rev. 5134a?seepr?9/05 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp s cl s da 8 -le a d pdip 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp s cl s da 8 -le a d s oic 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp s cl s da 8 -le a d t ss op
2 at24hc02b 5134a?seepr?9/05 figure 1. block diagram pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negat ive edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open-drain driven and may be wire-ored with any number of other open-drain or open collector devices. device/page addresses (a2, a1, a0): the a2, a1 and a0 pins are device address inputs that must be hardwired for the at24hc02b. as many as eight 2k devices may be addressed on a single bus system. (devic e addressing is discussed in detail under device addressing, page 8). absolute maximum ratings* operating temperature ........................................? 40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .........................................? 65 c to +150 c voltage on any pin with respect to ground ........................................ ? 1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma s ta rt s top logic
3 at24hc02b 5134a?seepr?9/05 write protect (wp): the at24hc02b has a wp pin that provides hardware data protection. the wp pin allows normal r ead/write operations when connected to ground (gnd). when the wp pin is connected to v cc , the write protection feature is enabled and operates as shown. table 2. write protect memory organization at24hc02b, 2k serial eeprom: the 2k is internally organized with 32 pages of 8 bytes each. random word addressing requires an 8-bit data word address. note: 1. this parameter is characterized and is not 100% tested. wp pin status part of the array protected 24hc02b at v cc upper half (1k) array at gnd normal read/write operations table 3. pin capacitance (1) applicable over recommended operating range from t ai = 25 c, f = 1.0 mhz, v cc = +1.8v symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , a 2 , scl) 6 pf v in = 0v
4 at24hc02b 5134a?seepr?9/05 note: 1. v il min and v ih max are reference only and are not tested. table 4. dc characteristics applicable over recommended operating range from: t ai = ? 40 c to +85 c, v cc = +1.8v to +5.5v (unless otherwise noted) symbol parameter test condition min typ max units v cc1 supply voltage 1.8 5.5 v v cc2 supply voltage 2.5 5.5 v v cc3 supply voltage 2.7 5.5 v v cc4 supply voltage 4.5 5.5 v i cc supply current v cc = 5.0v read at 100 khz 0.4 1.0 ma i cc supply current v cc = 5.0v write at 100 khz 2.0 3.0 ma i sb1 standby current v cc = 1.8v v in = v cc or v ss 0.6 3.0 a i sb2 standby current v cc = 2.5v v in = v cc or v ss 1.4 4.0 a i sb3 standby current v cc = 2.7v v in = v cc or v ss 1.6 4.0 a i sb4 standby current v cc = 5.0v v in = v cc or v ss 8.0 18.0 a i li input leakage current v in = v cc or v ss 0.10 3.0 a i lo output leakage current v out = v cc or v ss 0.05 3.0 a v il input low level (1) ? 0.6 v cc x 0.3 v v ih input high level (1) v cc x 0.7 v cc + 0.5 v v ol2 output low level v cc = 3.0v i ol = 2.1 ma 0.4 v v ol1 output low level v cc = 1.8v i ol = 0.15 ma 0.2 v
5 at24hc02b 5134a?seepr?9/05 note: 1. this parameter is ensured by characterization only. table 5. ac characteristics applicable over recommended operating range from t ai = ? 40 c to +85 c, v cc = +1.8v to +5.5v, cl = 1 ttl gate and 100 pf (unless otherwise noted) symbol parameter 1.8, 2.5, 2.7 5.0-volt units min max min max f scl clock frequency, scl 400 1000 khz t low clock pulse width low 1.2 0.4 s t high clock pulse width high 0.6 0.4 s t i noise suppression time 50 40 ns t aa clock low to data out valid 0.1 0.9 0.05 0.55 s t buf time the bus must be free before a new transmission can start 1.2 0.5 s t hd.sta start hold time 0.6 0.25 s t su.sta start setup time 0.6 0.25 s t hd.dat data in hold time 0 0 s t su.dat data in setup time 100 100 ns t r inputs rise time (1) 0.3 0.3 s t f inputs fall time (1) 300 100 ns t su.sto stop setup time 0.6 .25 s t dh data out hold time 50 50 ns t wr write cycle time 5 5 ms endurance (1) 5.0v, 25 c, byte mode 1m write cycles
6 at24hc02b 5134a?seepr?9/05 device operation clock and data transitions: the sda pin is normally pulled high with an exter- nal device. data on the sda pin may change only during scl low time periods (see figure 2). data change s during scl high periods will indica te a start or stop condition as defined below. figure 2. data validity start condition: a high-to-low transition of sda with scl high is a start condition that must precede any other command (see figure 3). figure 3. start and stop definition stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (see figure 3). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. . the eeprom sends a ?0? to acknowledge that it has received each word. this happens during the ninth clock cycle. standby mode: the at24hc02b features a low-power standby mode that is enabled: (a) upon power-up and (b) after the receipt of the stop bit and the completion of any internal operations. memory reset: after an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps:
7 at24hc02b 5134a?seepr?9/05 1. clock up to 9 cycles 2. look for sda high in each cycle while scl is high 3. create a start condition as sda is high. figure 4. bus timing figure 5. write cycle timing notes: 1. the write cycle time t wr is the time from a valid stop condition of a write s equence to the end of the internal clear/write cycle. t wr (1) stop condition start condition wordn ack 8th bit scl sda
8 at24hc02b 5134a?seepr?9/05 figure 6. output acknowledge device addressing the 2k eeprom device requires an 8-bit dev ice address word following a start condi- tion to enable the chip for a read or write operation, as shown in figure 7. figure 7. device address the device address word consists of a mandatory ?1?, ?0? sequence for the first four most significant bits as shown. this is common to all the eeprom devices. the next three bits are the a2, a1 and a0 device address bits for the 2k eeprom. these three bits must compare to their corresponding hardwired input pins. the eighth bit of the device address is the read/write operation select bit. a read opera- tion is initiated if this bit is high, and a wr ite operation is initiat ed if this bit is low. upon a compare of the device address, th e eeprom will output a ?0?. if a compare is not made, the chip will return to a standby state. write operations byte write: a write operation requires an 8-bit data word address following the device address word and acknowledgement. upon receipt of this address, the eeprom will again respond with a ?0? and then clock in the first 8-bi t data word. fo llowing receipt of the 8-bit data word, the eeprom will output a ?0? and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time, the eeprom enters an internally-timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle, and the eepr om will not respond until the write is complete, see figure 8 on page 9. msb 2k lsb 1 a 2 a 0 a 1 r/w 00 1
9 at24hc02b 5134a?seepr?9/05 figure 8. byte write page write: the 2k eeprom is capable of an 8-byte page write. a page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the fi rst data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2k) more data words. the eeprom will respond with a ?0? after each data word received. the microcontroller must terminate the page write sequence with a stop condi- tion, see figure 9. figure 9. page write the data word address lower three (2k) bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than eigh t (2k) data words are transmi tted to the eeprom, the data word address will ?roll over? and previous data will be overwritten. acknowledge polling: once the internally-timed write cycle has started and the eeprom inputs are disabl ed, acknowledge polling can be in itiated. this involves send- ing a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a ?0? allowing the read or write sequence to continue. s t a r t m s b m s b l s b s t o p w r i t e s da line device addre ss word addre ss data l s b a c k a c k a c k r / w s t a r t m s b s t o p w r i t e s da line device addre ss word addre ss (n) data (n) data (n + 1) data (n + x) l s b a c k a c k a c k a c k a c k r / w
10 at24hc02b 5134a?seepr?9/05 read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to ?1?. there are three read operations: current address read, random address read and sequential read. current address read: the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address ?roll over? during read is from the last byte of the last memory page to the first byte of the first page. the address ?roll over? during write is from the last byte of the cur- rent page to the first byte of the same page. once the device address with the read/write select bit set to ?1? is clocked in and acknowledged by the eeprom, the current addr ess data word is serially clocked out. the microcontroller does not respond with an input ?0? but does generate a following stop condition, see figure 10. figure 10. current address read random read: a random read requires a ?dummy? byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a ?0? but does generate a following stop condition, see figure 11. figure 11. random read sequential read: sequential reads are initiated by either a current address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom re ceives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will ?roll over? and the sequen- s t a r t r e a d m s b s t o p s da line device addre ss data l s b a c k n o a c k r / w s t a r t s t a r t m s b s t o p w r i t e r e a d s da line device addre ss dummy write word addre ss n device addre ss data n l s b a c k a c k a c k n o a c k r / w m s b l s b m s b l s b
11 at24hc02b 5134a?seepr?9/05 tial read will continue. th e sequential read operatio n is terminated when the microcontroller does not respond with a ?0? but does generate a following stop condition, see figure 12. figure 12. sequential read
12 at24hc02b 5134a?seepr?9/05 notes: 1. for 2.7v devices used in the 4.5v to 5.5v range, please re fer to performance values in the ac and dc characteristics ta ble. 2. ?u? designates green package + rohs compliant 3. available in waffle pack and wafer form; order as sl788 for inkless wafer form. bumped die available upon request. please contact serial eeprom marketing. at24hc02b ordering information (1) ordering code package operation range at24hc02b-10pu-1.8 (2) at24hc02bn-10su-1.8 (2) at24hc02b-10tu-1.8 (2) 8p3 8s1 8a2 lead-free/halogen-free/ industrial temperature ( ? 40 c to 85 c) at24hc02b-w1.8-11 (3) die sale industrial temperature ( ? 40 c to 85 c) package type 8p3 8-pin, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) 8a2 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) options ? 1.8 low voltage (1.8v to 5.5v)
13 at24hc02b 5134a?seepr?9/05 packaging information 8p3 ? pdip 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 8 p 3 , 8 -le a d, 0. 3 00" wide body, pl as tic d ua l in-line p a ck a ge (pdip) 01/09/02 8 p 3 b note s : 1. thi s dr a wing i s for gener a l inform a tion only; refer to jedec dr a wing m s -001, v a ri a tion ba, for a ddition a l inform a tion. 2. dimen s ion s a a nd l a re me asu red with the p a ck a ge s e a ted in jedec s e a ting pl a ne g au ge g s - 3 . 3 . d, d1 a nd e1 dimen s ion s do not incl u de mold fl as h or protr us ion s . mold fl as h or protr us ion s s h a ll not exceed 0.010 inch. 4. e a nd ea me asu red with the le a d s con s tr a ined to b e perpendic u l a r to d a t u m. 5. pointed or ro u nded le a d tip s a re preferred to e as e in s ertion. 6. b 2 a nd b3 m a xim u m dimen s ion s do not incl u de d a m ba r protr us ion s . d a m ba r protr us ion s s h a ll not exceed 0.010 (0.25 mm). common dimen s ion s (unit of me asu re = inche s ) s ymbol min nom max note d d1 e e1 e l b 2 b a2 a 1 n ea c b3 4 plc s a ? ? 0.210 2 a2 0.115 0.1 3 0 0.195 b 0.014 0.01 8 0.022 5 b 2 0.045 0.060 0.070 6 b3 0.0 3 0 0.0 3 9 0.045 6 c 0.00 8 0.010 0.014 d 0. 3 55 0. 3 65 0.400 3 d1 0.005 ? ? 3 e 0. 3 00 0. 3 10 0. 3 25 4 e1 0.240 0.250 0.2 8 0 3 e 0.100 b s c ea 0. 3 00 b s c 4 l 0.115 0.1 3 0 0.150 2 top view s ide view end view
14 at24hc02b 5134a?seepr?9/05 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. color a do s pring s , co 8 0906 title drawing no. r rev. note: 10/7/0 3 8s 1 , 8 -le a d (0.150" wide body), pl as tic g u ll wing s m a ll o u tline (jedec s oic) 8s 1 b common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a1 0.10 ? 0.25 the s e dr a wing s a re for gener a l inform a tion only. refer to jedec dr a wing m s -012, v a ri a tion aa for proper dimen s ion s , toler a nce s , d a t u m s , etc. a 1. 3 5 ? 1.75 b 0. 3 1 ? 0.51 c 0.17 ? 0.25 d 4. 8 0 ? 5.00 e1 3 . 8 1 ? 3 .99 e 5.79 ? 6.20 e 1.27 b s c l 0.40 ? 1.27 ? 0 ? 8 ? top view end view s ide view e b d a a1 n e 1 c e1 l
15 at24hc02b 5134a?seepr?9/05 8a2 ? tssop 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 5/ 3 0/02 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note d 2.90 3 .00 3 .10 2, 5 e 6.40 b s c e1 4. 3 0 4.40 4.50 3 , 5 a ? ? 1.20 a2 0. 8 0 1.00 1.05 b 0.19 ? 0. 3 0 4 e 0.65 b s c l 0.45 0.60 0.75 l1 1.00 ref 8 a2 , 8 -le a d, 4.4 mm body, pl as tic thin s hrink s m a ll o u tline p a ck a ge (t ss op) note s : 1. thi s dr a wing i s for gener a l inform a tion only. refer to jedec dr a wing mo-15 3 , v a ri a tion aa, for proper dimen s ion s , toler a nce s , d a t u m s , etc. 2. dimen s ion d doe s not incl u de mold fl as h, protr us ion s or g a te bu rr s . mold fl as h, protr us ion s a nd g a te bu rr s s h a ll not exceed 0.15 mm (0.006 in) per s ide. 3 . dimen s ion e1 doe s not incl u de inter-le a d fl as h or protr us ion s . inter-le a d fl as h a nd protr us ion s s h a ll not exceed 0.25 mm (0.010 in) per s ide. 4. dimen s ion b doe s not incl u de d a m ba r protr us ion. allow ab le d a m ba r protr us ion s h a ll b e 0.0 8 mm tot a l in exce ss of the b dimen s ion a t m a xim u m m a teri a l condition. d a m ba r c a nnot b e loc a ted on the lower r a di us of the foot. minim u m s p a ce b etween protr us ion a nd a dj a cent le a d i s 0.07 mm. 5. dimen s ion d a nd e1 to b e determined a t d a t u m pl a ne h. 8 a2 b s ide view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indic a tor thi s corner e e
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